1. Field of the Invention
The present invention relates to an instruction cache and, more particularly, to a decoded instruction cache for an instruction unit.
2. Description of the Related Art
High performance computers typically use an instruction layout which is encoded. For example, in Very-Large-Instruction-Word (VLIW) computers, multiple instructions are encoded within an instruction-word. When an instruction-word is decoded, several instructions which are to be simultaneously executed in a pipeline are obtained. Given that the instruction layout of high performance computers is long, memory storage for the instructions is conserved if the instructions are not decoded until the instructions are issued. However, this approach requires an extra clock cycle or pipeline stage to decode the instructions after they are issued from the instruction cache. Another approach is to decode the instructions for only the later stages in the memory hierarchy. Namely, instructions stored in a secondary cache would be in encoded form, but would be decoded before stored in a primary cache.
The problem is more severe in computers which use a variable length instruction, yet concurrently issue multiple operations. In this case, even if an extra clock cycle or pipeline stage for decoding is avoided, determination of the address of the instruction to be issued next requires an extra cycle or stage in the pipeline. The next instruction could be a target address of a branch instruction or a sequential address. The sequential address can itself vary depending on how many operations are issued by the previous instruction.
Thus, there is a need for a mechanism to determine the address for a next instruction without having to use an extra clock cycle or an additional stage in a pipeline.